Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modem personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate.
NOR and NAND flash memory devices are two common types of flash memory devices, so called for the logical form of the basic memory cell configuration in which each is arranged. Typically, for NOR flash memory devices, the control gate of each memory cell of a row of the array is connected to a word-select line, and the drain region of each memory cell of a column of the array is connected to a bit line. The memory array for NOR flash memory devices is accessed by a row decoder activating a row of floating-gate memory cells by selecting the word-select line coupled to their gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current, depending upon their programmed states, from a coupled source line to the coupled column bit lines.
The array of memory cells for NAND flash memory devices is also arranged such that the control gate of each memory cell of a row of the array is connected to a word-select line. However, each memory cell is not directly coupled to a column bit line by its drain region. Instead, the memory cells of the array are arranged together in strings (often termed NAND strings), typically of 32 each, with the memory cells coupled together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word-select line coupled to a control gate of a memory cell. In addition, the word-select lines coupled to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
The floating-gate field-effect transistors forming the floating-gate memory cells of NOR and NAND memory devices typically include a tunnel dielectric layer, e.g., a tunnel oxide, disposed on a substrate, such as silicon. A floating gate layer, e.g., a first polysilicon layer, overlies the tunnel dielectric layer, and an interlayer dielectric layer overlies the floating gate layer. A control gate (or word line) overlies the interlayer dielectric layer and usually consists of a second polysilicon layer disposed on the interlayer dielectric layer and a conductive layer, such as a metal or polycide layer, disposed on the second polysilicon layer. A protective cap layer typically overlies the metal or polycide layer.
For NOR memory devices field-effect transistors are often disposed about the periphery of the NOR memory array and are connected to the NOR memory array for controlling operation of the NOR memory array. For example, such field-effect transistors are often used to access rows and columns of the NOR memory array. For NAND memory devices, field-effect transistors are often connected on either end of the NAND strings and used as select gates.
Typically, some field-effect transistors are formed concurrently with the floating-gate transistors and thus the field-effect transistors often have the same layers as the floating-gate transistors. For example, the field-effect transistors include the first polysilicon layer overlying a gate dielectric layer disposed on the substrate, the interlayer dielectric layer overlying the first polysilicon layer, the second polysilicon layer overlying the interlayer dielectric layer, the metal or polycide layer overlying the second polysilicon layer, and the protective cap layer typically overlying the metal or polycide layer. However, it is desirable that the field-effect transistors and the floating-gate transistors operate differently. That is, a floating gate should not hinder the field-effect transistors. Therefore, the floating gate needs to be eliminated.
Shorting the first and second polysilicon layers together is one way to eliminate the floating gate. For NAND memory devices, shorting the first and second polysilicon layers together is usually accomplished by forming a metal or polycide strap on the protective cap layer. A first conductor is passed through the protective cap layer, the metal or polycide layer, the second polysilicon layer, and the interlayer dielectric layer and is connected between the strap and first polysilicon layer. A second conductor is passed through the protective cap layer and the metal or polycide layer and is connected between the strap and second polysilicon layer so that the strap shorts the first and second polysilicon layers together. The shorted-together first and second polysilicon layers typically forms a select line that extends over several columns of the NAND array. However, this method of shorting the first and second polysilicon layers together effectively shorts the first and second polysilicon layers together at a single region of the select line. This results in select lines with relatively high resistance because the select lines are primarily of polysilicon. The relatively high resistance acts to slow down the operation of the select gates along the select line. Moreover, this method of shorting is not normally used for the field-effect transistors that are disposed about the periphery of NOR memory devices, as the field-effect transistors generally do not share a common control gate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative NOR and NAND memory devices.